NXP Semiconductors /MIMXRT1021 /IOMUXC_SNVS_GPR /GPR3

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Interpret as GPR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LPSR_MODE_ENABLE_0)LPSR_MODE_ENABLE 0 (DCDC_STATUS_CAPT_CLR)DCDC_STATUS_CAPT_CLR 0 (POR_PULL_TYPE_0)POR_PULL_TYPE 0 (DCDC_IN_LOW_VOL_0)DCDC_IN_LOW_VOL 0 (DCDC_OVER_CUR_0)DCDC_OVER_CUR 0 (DCDC_OVER_VOL_0)DCDC_OVER_VOL 0 (DCDC_STS_DC_OK_0)DCDC_STS_DC_OK

DCDC_OVER_VOL=DCDC_OVER_VOL_0, DCDC_IN_LOW_VOL=DCDC_IN_LOW_VOL_0, DCDC_STS_DC_OK=DCDC_STS_DC_OK_0, LPSR_MODE_ENABLE=LPSR_MODE_ENABLE_0, DCDC_OVER_CUR=DCDC_OVER_CUR_0, POR_PULL_TYPE=POR_PULL_TYPE_0

Description

GPR3 General Purpose Register

Fields

LPSR_MODE_ENABLE

Set to enable LPSR mode.

0 (LPSR_MODE_ENABLE_0): SNVS domain will reset when system reset happens

1 (LPSR_MODE_ENABLE_1): SNVS domain will only reset with SNVS POR

DCDC_STATUS_CAPT_CLR

DCDC captured status clear

POR_PULL_TYPE

POR_B pad control

0 (POR_PULL_TYPE_0): 100 Ohm pull up enabled for POR_B always

1 (POR_PULL_TYPE_1): Disable pull in SNVS mode, 100 Ohm pull up enabled otherwise

2 (POR_PULL_TYPE_2): Disable pull of POR_B always

3 (POR_PULL_TYPE_3): 100 Ohm pull down enabled in SNVS mode, 100 Ohm pull up enabled otherwise

DCDC_IN_LOW_VOL

DCDC_IN low voltage detect.

0 (DCDC_IN_LOW_VOL_0): DCDC_IN is ok

1 (DCDC_IN_LOW_VOL_1): DCDC_IN is too low

DCDC_OVER_CUR

DCDC output over current alert

0 (DCDC_OVER_CUR_0): No over current detected

1 (DCDC_OVER_CUR_1): Over current detected

DCDC_OVER_VOL

DCDC output over voltage alert

0 (DCDC_OVER_VOL_0): No over voltage detected

1 (DCDC_OVER_VOL_1): Over voltage detected

DCDC_STS_DC_OK

DCDC status OK

0 (DCDC_STS_DC_OK_0): DCDC is ramping up and not ready

1 (DCDC_STS_DC_OK_1): DCDC is ready

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